DSP for FPGA: Simple FIR Filter in Verilog

Frequency response of a low pass filter.

The main focus of this project is on the implementation of a FIR in HDL (Verilog specifically, but the concept can be easily translated to VHDL), which can be broken down into three main logic components: a circular buffer to buffer each sample into that truly compensates the latency of the serial input, the multipliers for every tap’s coefficient value and the accumulator register for the summing result from each tap’s output.

Things used in this project

Digilent Arty Z7–20

USB-A to Micro-USB Cable

AMD Vivado Design Suite

PROCEDURE:

Create Design File for FIR Module

For this FIR, I selected the input sample and coefficients registers to each be 16 bits wide and my output sample register to be 32 bits. If I had used 16-bit input samples with 8-bit taps, the product would be 24 bits wide (the widths of the two values being multiplied add to…